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MT6625L Datasheet资料数据手册
原文资料内容介绍：
MT6625L TOP Building Blocks
1.Reference Clock
The reference clock source needs to satisify 0.8 Vpp with rising/falling time of 5 nsec and phase noise of 149 dBc/Hz at 100-kHz offset frequency. The clock buffers draw 90 μA. The first stage buffer employs ac-coupled architecture to ensure proper amplification even with weak input clock whose swing is less than thresh voltage of transistors. There is a tie-low switch in the buffer to each block (i.e. WBT, GPS, FM, THADC and DIG) to guarantee well-defined voltage for input ports of blocks mentioned above.
2.Thermal ADC
A low-speed ADC converts the output of thermal sensor to 8-cycle-average or 16-cycle-average ADC code which represents the current chip temperature near the THADC. The temperature coveragerange is between -40 and 120 degree Celsius. The chip top control may do corresponding adjustment (such as PA/TX gain switching) based on such temperature information.
3.Always-on LDO
A low-power bandgap reference provides biasing currents for internal LDO as well as reference voltages for THADC’s temperature sensing. An always-on LDO provides an internal 1.2V voltage to digital circuits from an external supply of 1.8V. In normal operation, the BG circuit generates the reference voltage for the LDO. In sleep mode, the BG+LDO consumes a small quiescent current of ~25uA. The LDO output voltage and driving capability are programmable.
4.Wi-Fi/BT
MT6625L Wi-Fi/BT is a high performance and highly-integrated dual-band RF transceiver fully compliant with IEEE 802.11 a/b/g/n and Bluetooth v2.1+EDR/v3.0+HS/v4.1 LE standards. A novel RF front-end topology is implemented to achieve maximum hardware sharing between 2.4GHz/5GHz WiFi and Bluetooth with integrated TR-switches. MT6625L also features a self calibration scheme to compensate the process and temperature variation to maintain high performance. The calibration is performed automatically right after the system boot-up.
5.FM
6.GPS
7.IPD
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