十六位加法计数器test bench程序

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                
USE ieee.std_logic_unsigned.all;                                  ENTITY H1_test IS
END H1_test;
ARCHITECTURE ONE OF H1_test IS
-- constants                                                 
-- signals                                                   
SIGNAL CLK1 : STD_LOGIC;
SIGNAL DIN1 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL DOUT1 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL EN1 : STD_LOGIC;
SIGNAL R1 : STD_LOGIC;
SIGNAL S1 : STD_LOGIC;
CONSTANT CLK_P: TIME:= 250 ns;---定义时间常数
--例化
COMPONENT H1       PORT (CLK : IN STD_LOGIC;DIN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);DOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);EN : IN STD_LOGIC;R : IN STD_LOGIC;S : IN STD_LOGIC);
END COMPONENT;BEGINU1 : H1 PORT MAP (CLK => CLK1,DIN => DIN1,DOUT => DOUT1,EN => EN1,R => R1,S => S1   );--
PROCESS   --时钟进程                                               
BEGIN                   
CLK1<='0';  WAIT FOR CLK_P;
CLK1<='1';  WAIT FOR CLK_P;--返回                                                  
END PROCESS;R1<='0',     '1' AFTER 610 ns,'0' AFTER 880 ns;   --复位EN1<='0',    '1' AFTER 300 ns,  '0' AFTER 7000 ns, '1' AFTER 7500 ns;--计数S1<='0',     '1' AFTER 4000 ns,'0' AFTER 4500 ns;    --置数DIN1<="0101", "0011" AFTER 850 ns,  "0111"  AFTER  6000 ns;                                   
END ONE;