设计一个串行数据检测器。要求是：连续4 个或4 个以上为1 时输出为1，其他输入情况下为0

状态转换图如下：

//******************************seqdet.v**************************************

module seqdet(x,z,clk,rst,state);
input x,clk,rst;
output z;
output[2:0] state;
reg[2:0] state;
wire z;
parameter IDLE=3'd0,A=3'd1,B=3'd2,C=3'd3,D=3'd4;

assign z = ((state==C && x==1)||(state==D && x==1))?1:0 ;

always @(posedge clk)
begin
    if(!rst) state<=IDLE;
    else
        casex(state)
            IDLE: if(x==1) state<=A;
                  else state<=IDLE;
            A:    if(x==1) state<=B;
                  else state<=IDLE;
            B:    if(x==1) state<=C;
                  else state<=IDLE;
            C:    if(x==1) state<=D;
                  else state<=IDLE;
            D:    if(x==1) state<=D;
                  else state<=IDLE;
            default: state<=IDLE;
        endcase
end

endmodule
//******************************seqdet_TB.v**************************************

`timescale 1ns / 1ns

module seqdet_TB;
reg clk, rst,x;
wire[2:0] state;
wire z;
always #10 clk=~clk;
always @(posedge clk)
    begin
        x<={$random}%2;
    end
initial
    begin
        clk=0;
        rst=1;
        #2 rst=0;
        #10 rst=1;
        #1000 $stop;
    end
seqdet m(x,z,clk,rst,state);

endmodule