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带有握手信号的无符号数乘法verilog+ testbench 代码
uumultiplier.v
module uumultiplier #(parameter NUMBER1 = 8 ,parameter NUMBER2 = 10)(input [NUMBER1-1 : 0] input1 ,input [NUMBER2-1 : 0] input2 ,input clk ,input rst_n ,input begin_en ,output reg finish_en ,output reg [NUMBER1+NUMBER2 : 0] out);//======================================================================================\// define parameter and internal signal \//======================================================================================\reg [NUMBER1+NUMBER2 : 0] out1 ;//==========================================================================================\// next is main code \\//===========================================================================================\\
always@(posedge clk or negedge rst_n)beginif(rst_n == 0)beginout <= 0 ;endelse if(begin_en && finish_en )beginout <= input1 * input2 ;endelseout <= out ;endalways@(posedge clk or negedge rst_n )beginif(rst_n == 0)beginout1 <= 0 ;endelseout1 <= out ;endalways@(posedge clk or negedge rst_n)beginif(rst_n == 0)beginfinish_en <= 1'b1 ;endelse if(out != out1)beginfinish_en <= 1'b1 ;endelsefinish_en <= 1'b0 ;endendmodule
uumultiplier_tb.v
module uumultiplier_tb #(parameter NUMBER1 = 8 ,parameter NUMBER2 = 10 );reg [NUMBER1-1 : 0] input1 ;
reg [NUMBER2-1 : 0] input2 ;
reg clk ;
reg rst_n ;
reg begin_en ;
wire finish_en ;
wire [NUMBER1+NUMBER2 : 0] out ;uumultiplier#(.NUMBER1 ( NUMBER1 ),.NUMBER2 ( NUMBER2 )
)u_uumultiplier(.input1 ( input1 ),.input2 ( input2 ),.clk ( clk ),.rst_n ( rst_n ),.begin_en ( begin_en ),.finish_en ( finish_en ),.out ( out )
);always #5 clk = ~clk ;initial begin clk = 0 ;rst_n = 0 ;input1 = 1 ;input2 = 1 ;begin_en = 1 ;#20rst_n = 1 ;input1 = 10 ; input2 = 8 ;#20input1 = 12 ; input2 = 8 ;#20 input1 = 1 ; input2 = 8 ;#20input1 = 3 ; input2 = 5 ;end
endmodule
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