modelsim仿真环境的搭建

本文主要是介绍modelsim仿真环境的搭建，希望对大家解决编程问题提供一定的参考价值，需要的开发者们随着小编来一起学习吧！

相对gui图形界面的操作，脚本执行更方便。

注意：

如果有include语句。那么就增加+incdir+路径。
如果想用电路视图。那么就加入参数：vsim -debugDB

vlog -work work -vopt +incdir+D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/ACC.V \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/ALU.V \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/bus_arbiter.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/cmd_ack.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/cmd_decoder.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/cmd_detector.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/cmd_generator.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/cmd_internal_reg.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/command_if.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/CONTROL.V \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/data_cache_way0.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/data_cache_way1.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/data_cache_way2.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/data_cache_way3.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/data_in_reg.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/data_port.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/dma_cntrl.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/dma_fifo.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/dma_internal_reg.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/flash_ctrl.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/fsm.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/instruction_cache_way0.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/instruction_cache_way1.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/instruction_cache_way2.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/instruction_cache_way3.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/IR.V \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/k9f1g08u0m.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/lru_data_cache.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/lru_instruction_cache.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/MEM.V \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/MUX12.V \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/MUX16.V \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/oe_generator.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/PC.V \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/ras_cas_delay.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/ref_ack.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/ref_timer.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/risc.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/sdram.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/sdram_cntrl.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/sdram_mux.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/sdram_port.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/sdramctrl_rtl.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/soc.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/timer.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/Top_level_tb.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/other.v \D:/tools/perl/perl-study/verilog/embedded_risc/trunk/Verilog/uart.vvsim -debugDB -lib work testbench