嵌入式linux开发 (二十五) 内存管理(7) 其他芯片在硬件上对内存的管理

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讨论的是芯片硬件对内存的管理,包括芯片中固化的代码

N32905U1DN

总介

	ARM926EJ-S 32-bit RISC CPU with 8KB I-Cache & 8KB D-CacheFrequency up to 200MHz@1.8V core power operation voltageJTAG interface supported for development and debugginghttps://bbs.21ic.com/icview-542928-1-1.html

内部:

	8KB internal SRAM // 0xFF00_0000 - 0xFF00_1FFF16KB IBR internal booting ROM(IBR) // 0xFFFF_0000 - 0xFFFF_FFFFIBR booting messages displayed by UART console for debugging supported

外部:

	Different system booting modes supported:Memory cardSD cardSD-to-NAND flash bridgeRaw NAND FlashSPI FlashUSBSDRAM:0x0000_0000 - 0x3FFF_FFFF

boot

没有搜到boot资料
猜测 启动分为 一级启动 和 二级启动
----------------------------- 一级启动
从IBR internal booting ROM(IBR)启动,此时使用internal SRAM,此时会打印log到UART console
----------------------------- 二级启动
IBR根据boot配置加载对应的设备的前8KB(因为SRAM有8KB)数据进SRAM,然后启动代码

s3c6410

总介

The ARM subsystem is based on the ARM1176JZF-S coreThe memory system has dual external memory ports, DRAM and Flash/ROM. The DRAM port can be configured to support mobile DDR, DDR, mobile SDRAM and SDRAM. The Flash/ROM port supports NOR-Flash, NAND-Flash,OneNAND, CF and ROM type external memory.

内部

srom: // 32KB0x0800_0000 0x0BFF_FFFF 64MB Internal ROM
sram: // 8KB0x0C00_0000 0x0FFF_FFFF 64MB Stepping Stone (Boot Loader)0x0000_0000 0x07FF_FFFF 128MB Booting Device Region by XOM Setting Mirrored Region ???

外部

DRAM:DRAM Controller of the Memory Port10x5000_0000 0x5FFF_FFFF 256MB0x6000_0000 0x6FFF_FFFF 256MB
FLASH:supports NOR-Flash, NAND-Flash,OneNAND, CF and ROM type external memory.

boot

The operating mode is mainly classified into six categories according to the boot device. The boot device can be among SROM, NOR, OneNAND, MODEM and Internal ROM// 对于不同的启动配置(OM[4:0]决定),memory map不同
// 没找到合适的官方boot资料,以下来源于网络
(1) 上电后首先运行iRom（BL0）内的代码，主要完成时钟和看门狗等外围器件的初始化。
(2) 拷贝SD卡或者NnadFlash中的前4k(BL1)代码到片内ram(垫脚石)去运行，主要工作是配置主存储器SDRAM。并将剩余的BL1和BL2加载到SDRAM上。 // 这里有问题??应该是8KB吧,没找到资料,ε=(´ο｀*)))唉
(3) 完成后将程序的入口跳转到SDRAM中的BL2继续运行。并将存储设备上的OS加载到SDRAM运行。
(4) 将程序的入口跳转到拷贝到SDRAM上的OS的入口进行运行。

s5pv210

总介

It integrates the ARM Cortex-A8 core, which implements the ARM architecture V7-A with supporting peripherals.
S5PV210 has an interface to external memory that is capable of sustaining heavy memory bandwidths required in
high-end communication services. The memory system has Flash/ ROM external memory ports for parallel access and DRAM port to meet high bandwidths.DRAM controller supports LPDDR1 (mobile DDR), DDR2, or LPDDR2.Flash/ ROM port supports NAND Flash, NOR-Flash, OneNAND, SRAM, and ROM type external memory.

内部

IROM: 64KB0xD000_0000 0xD000_FFFF 64KB IROM
IRAM: 96KB0xD002_0000 0xD003_7FFF 96KB IRAM0x0000_0000 0x1FFF_FFFF 512MB Boot area  Mirrored region depending on the boot mode.

外部

DRAM:0x2000_0000 0x3FFF_FFFF 512MB DRAM 00x4000_0000 0x7FFF_FFFF 1024MB DRAM 1
FLASH:supports NAND Flash, NOR-Flash, OneNAND, SRAM, and ROM type external memory

boot

The boot loader is largely composed of iROM, first and second boot loaders. 
The characteristics of these boot loaders are:• iROM code: Contains small and simple code, which is platform-independent and stored in internal memory• First boot loader: Contains small and simple code, which is platform-independent and stored in externalmemory device. Related to secure booting.• Second boot loader: Contains complex code, which is platform-specific and stored in external memory device.The booting device can be chosen from following list:• General NAND Flash memory• OneNAND memory• SD/ MMC memory (such as MoviNAND and iNAND)• eMMC memory• eSSD memory• UART and USB devices

exynos4412

总介

ARM Cortex-A9 based Quad CPU Subsystem with NEON 32/32/32/32 KB I/D Cache, 1 MB L2 Cache Operating frequency up to 1.4 GHz64 KB ROM for secure booting and 256 KB RAM for security function

内部

	0x0000_0000 0x0001_0000 64 KB iROM0x0202_0000 0x0206_0000 256 KB iRAM

外部

	The memory system has dedicated DRAM ports and Static Memory port. RAM: The dedicated DRAM ports support LPDDR2 interface for high bandwidth. FLASH: Static Memory Port supports NOR Flash and ROM type external memory and components.

boot：

	Due to the recent increase in the prices of NOR flash memory and the moderately priced DRAM, and NAND flash,customers prefer to execute boot code on NAND flash and execute the main code on DRAM.The boot code in Exynos 4412 can be executed on external NAND flash. It copies NAND flash data to DRAM. To validate the NAND flash data, Exynos 4412 includes hardware Error Correction Code (ECC). After the NAND flash content is copied to DRAM, main program will be executed on DRAMThe features of NAND flash controller are: Auto boot: The boot code is transferred to internal SRAM during reset. After the transfer, the boot code will be executed on the SRAM.OM[5:1] 配置1st device 和 2nd device // If it fails to download BL1 from the first booting device, the iROM code tries to download BL1 from the second booting device (USB or SDMMC_CH2).General NAND flash memorySD/MMC memory cardeMMC memoryUSB deviceThe boot loader is comprises the first and the second boot loaders. The characteristics of these boot loaders are: iROM: It is a small and simple code to initiate SOC. It is implemented on internal ROM of SOC. First boot loader (BL1): It is chip-specific and stored in external memory device. Second boot loader (BL2): It is platform-specific and stored in external memory device. 三星不提供 BL1 BL2 
-------------------具体启动流程 iROM is placed in internal 64 KB ROM. It initializes basic system functions such as clock and stack. iROM loads BL1 image from a specific booting device to internal 256 KB SRAM. The booting device isselected by Operating Mode (OM) pins. According to the secure boot key values, iROM may do an integritycheck on BL1 image. BL1 initializes system clock, and DRAM controller. After initializing DRAM controller, it loads OS image fromthe booting device to DRAM. According to the secure boot key values, BL1 can do an integrity check on theOS image. After the booting completes, BL1 jumps to the operating system.

RK-3288

总介

Quad-core ARM Cortex-A17 MPCore processor, a high-performance, low-power and cached application processor

内部

 Internal on-chip memory
 20KB BootRom
 100KB internal SRAM for security and non-security access, detailed size is programmable

外部

 External off-chip memory①DRAM:DDR3 LPDDR2 LPDDR3FLASH:Nand SD eMMC

boot

RK3288 provides system boot from off-chip devices such as SDMMC card, 8bits async nand flash or toggle nand flash, SPI nor or nand, and eMMC memory. When boot code is not ready in these devices, also provide system code download into them by USB OTG interface.
启动过程为二级启动(boot loader)
一级启动:从bootrom启动,根据配置加载设备前100KB进sram,并执行sram中的代码
二级启动:用户代码:一般为初始化ddr,然后拷贝二级启动设备上的全部代码进入ddr.然后跳转到ddr.

其他资料不全的芯片

hi3531a R16 mt2503

总结

启动过程是随着时间的推移不断变化的

单片机芯片,以stm32为典型:映射主flash到0x00000000 ,然后从0x00000000 启动
AP 芯片,以三星家族为例s3c2440 -> s3c6410 -> s5pv210 -> exynos4412s3c2440: 无srom,nandflash搬运到sram(4KB)启动s3c6410: 有srom(Internal ROM,32KB),从srom启动,然后加载二级启动设备前8KB代码到srams5pv210: 有srom(Internal ROM,64KB),从srom启动,然后加载二级启动设备前96KB代码到sramexynos4412: 有srom(Internal ROM,64KB),从srom启动,然后加载二级启动设备前256KB代码到sram

当前主流启动流程(2020-04-20)

单片机芯片,以stm32为典型:映射主flash到0x00000000 ,然后从0x00000000 启动
AP芯片,有srom(Internal ROM,64KB),从srom启动,然后加载二级启动设备前256KB代码到sram(sram大小:256KB)且SROM大小和SRAM大小目前应该已经定型,不会再增加了.且SROM中由厂家固化的代码会做越来越多的事情,例如I.MX6ULL 中新增了初始化DDR和从启动设备中搬移代码到DDR.